The present invention is related in general to the field of semiconductor devices and processes, and more specifically to plastic chip-scale packages which house passive electronic components integrated with the circuit embedded in the semiconductor chip.
As portable appliances continue to integrate more functionality into smaller packages, minimization of total board space becomes more critical. On the one hand, progress in silicon technology continues to successfully integrate more and more functionality into the silicon chip for numerous products. On the other hand, a number of functions stubbornly resist the desired integration. For example, some functionality such as regulator bypass capacitance, Phase-Locked-Loop (PLL) loop filter components, and impedance matching components, cannot be efficiently integrated into current or planned silicon process technologies.
In highly integrated solutions, the placement of external components, such as regulator bypass capacitors, impacts the overall performance of the solution. If one could integrate some of these components within the product package, one could minimize parasitic effects related to inductances, capacitances and resistances, and thus offer optimized product performance.
Furthermore, in high performance digital and analog integrated circuit (IC) products, it is desirable to minimize the number of pins/leads that must be connected to other components on the printed circuit board. Integrating functional blocks, such as low-drop-out voltage regulators, and their requisite external components (for instance, bypass capacitors) allows the IC designer to distribute these functions more evenly within the IC, and in some cases to increase the number of individual bypass components. Electrical isolation between functional blocks with the IC can thus be improved. This can be achieved without increasing the number of external components, or increasing the footprint of the chip-scale package.
An urgent need has, therefore, arisen for a low-cost, reliable structure and method technology to provide integration of passive components within plastic semiconductor packages, especially chip-scale packages. The system should provide simple, no-cost-added integration especially for high-growth products such as wireless products and digital signal processors. It should be flexible and tolerant for process variations such as wire bonding versus flip-chip assembly, transfer molding versus potting encapsulation, or solder ball versus pin connections to outside parts.
The structure and method should be applicable to a wide spectrum of design, material and process variations, leading to significant savings of silicon and fabrication processes, as well as to improved device characteristics and reliability and process yield. Preferably, these innovations should be accomplished using the installed process and equipment base so that no investment in new manufacturing machines is needed.
A semiconductor device is disclosed having passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment.
In a preferred embodiment of the invention, a plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers comprise a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing lines terminate in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip. The chip is attached to the central substrate area and electrically connected to the first plurality of contact pads, respectively, whereby the passive components are integrated with the IC. Plastic encapsulation material surrounds the chip, first plurality of contact pads, and passive components such that the outline of the material is approximately the same as the outline of the chip.
It is an aspect of the present invention to significantly reduce the number of external components needed for high performance operation of the IC by integrating them into the plastic device package.
Another aspect of the invention is to reduce the board footprint of the device.
Another aspect of the invention is to optimize the distribution of functional blocks (such as LDO regulators) without increasing external pin count, resulting in optimal functional block electrical isolation.
Another aspect of the invention is to provide design and layout concepts, process methods, and assembly alternatives which are flexible so that they can be applied to many families of semiconductor IC products, and are general, so that they can be applied to several generations of products.
Another aspect of the invention is to provide a low-cost and uncomplicated process for fabrication, testing and assembly, using thin, flexible, patternable and adhesive plastic films.
Another aspect of the invention is to use only design concepts and processes most commonly used and accepted in the fabrication of IC devices, thus avoiding the cost of new capital investment and using the installed fabrication equipment base.
These aspects have been achieved by the teachings of the invention concerning design concepts and process flow suitable for mass production. Various modifications have been successfully employed to satisfy different selections of product materials and packages.